Postdoctoral Researcher · Electrical & Computer Engineering

Full-Stack IC Design &
High-Performance Chip Architect

I build energy-efficient computing systems across the full stack, from algorithms and architecture to RTL, ASIC implementation, FPGA validation, and post-silicon characterization.

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Miao Sun, Ph.D.

Postdoctoral Researcher
Washington State University

Former Postdoctoral Researcher, UW–Madison
Ph.D., Microelectronics, Fudan University

Google Scholar Profile

Research Interests

Domain-Specific Accelerators Computer Architecture Digital VLSI Design ASIC / FPGA Systems Chiplet-Based AI Systems LLM Inference Acceleration Edge AI SoCs Hardware/Software Co-Design Mixed-Signal dToF / LiDAR Systems Sensor-Fusion Hardware Thermal & PDN Management Near-Sensor Computing

Academic Appointments

Washington State University · Postdoctoral Researcher

Dec. 2025 – Present

Research focus: thermal-aware computer architecture, power delivery optimization, and chiplet-based AI systems for next-generation heterogeneous computing platforms.

Developing efficient hardware architectures for scalable LLM inference on heterogeneous chiplet platforms.

University of Wisconsin–Madison · Postdoctoral Researcher

Feb. 2025 – Dec. 2025

Proposed LEXI, a lossless exponent coding architecture that reduces inter-chiplet communication overhead for hybrid LLM inference while preserving numerical accuracy.

Designed eMamba, an efficient hardware accelerator architecture for Mamba models on edge platforms, optimizing memory access, computation efficiency, and system throughput.

Nanyang Technological University · Research Fellow

Aug. 2023 – Feb. 2025

Developed high-frame-rate LiDAR imaging systems integrating metalens optics, dToF sensing, event cameras, and edge AI hardware.

Education

Fudan University

Ph.D. in Microelectronics · 2018 – 2023

Dissertation research on edge-computing SoCs, neural network accelerators, and dToF LiDAR systems.

Southwest University

B.Eng. in Electrical & Electronic Engineering · 2014 – 2018

Selected Silicon Tape-Outs & Hardware Implementations

40 nm LiDAR AI SoC

2 TOPS/W · IEEE TCAS-II

Depth-completion neural network accelerator SoC implemented in 40 nm CMOS. Led full design flow from RTL implementation to FPGA validation, tape-out, and post-silicon characterization.

GlobalFoundries 22 nm Mamba Accelerator

State-Space Model Acceleration

Designed a domain-specific hardware accelerator for Mamba state-space models through RTL design, physical implementation, timing closure, and 22 nm ASIC implementation.

dToF / SPAD LiDAR Hardware

128×80 SPAD · Addressable VCSEL

Co-developed adaptive beam-steering LiDAR hardware with on-chip and edge AI support for intelligent sensing and sensor-fusion systems.

Selected Publications

Selected Journal Publications

  1. Miao Sun, et al., “A 40nm 2TOPS/W Depth-Completion Neural Network Accelerator SoC with Efficient Depth Engine for Realtime LiDAR Systems,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 5, pp. 1704–1708, 2023.
  2. Miao Sun, Y. Wu, L. Cui, et al., “228×304 200-mW LiDAR Based on a Single-Point Global-Depth dToF Sensor and RGB-Guided Super-Resolution Neural Network,” Optics Letters, 2023.
  3. S. Zhuo, T. Xia, L. Zhao, Miao Sun, et al., “Solid-State dToF LiDAR System Using an Eight-Channel Addressable, 20-W/Ch Transmitter, and a 128×128 SPAD Receiver with SNR-Based Pixel Binning and Resolution Upscaling,” IEEE Journal of Solid-State Circuits, vol. 58, no. 3, pp. 757–770, 2023.
  4. Y. Wu, Miao Sun, et al., “An Adaptive Beam-Steering dToF LiDAR System Using Addressable Multi-Channel VCSEL Transmitter, 128×80 SPAD Sensor, and ML-Based Edge-Computing Object Detection,” IEEE Transactions on Circuits and Systems I: Regular Papers, 2025.
  5. W. Lu, M. Lu, X. Zhang, Z. Lu, Miao Sun, et al., “A Fully Probabilistic Model for Sigmoid Approximation and Its Hardware-Efficient Implementation,” IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 71, no. 8, pp. 3775–3786, 2024.
  6. J. Ma, S. Zhuo, L. Qiu, et al., including Miao Sun, “A Review of ToF-Based LiDAR,” Journal of Semiconductors, vol. 45, no. 10, 101201, 2024.
  7. S. Zhuo, Y. Wang, T. Xia, et al., including Miao Sun, “A 200 MHz 14 W Pulsed Optical Illuminator with Laser Driver ASIC and On-Chip DLL-Based Time Interpolator for Indirect Time-of-Flight Applications,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 70, no. 2, pp. 396–400, 2023.
  8. T. Xia, X. Chen, Y. Wu, et al., including Miao Sun, “An 8-A Sub-1ns Pulsed VCSEL Driver IC with Built-In Pulse Monitor and Automatic Peak Current Control for Direct Time-of-Flight Applications,” IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 11, pp. 4193–4197, 2022.
  9. J. Wang, J. Li, Y. Wu, et al., including Miao Sun, “A 256×256 LiDAR Imaging System Based on a 200 mW SPAD-Based SoC with Microlens Array and Lightweight RGB-Guided Depth Completion Neural Network,” Sensors, vol. 23, no. 15, 6927, 2023.
  10. L. Cui, J. Li, S. Zhuo, et al., including Miao Sun, “80×120 AI-Enhanced LiDAR System Based on a Lightweight Intensity–RGB–dToF Sensor Fusion Neural Network Deployed on an Edge Device,” Optics Letters, vol. 48, no. 23, pp. 6192–6195, 2023.
  11. Miao Sun, S. Zhuo, and P. Y. Chiang, “Multi-Scale Histogram-Based Probabilistic Deep Neural Network for Super-Resolution 3D LiDAR Imaging,” Sensors, vol. 23, no. 1, 420, 2023.

Selected Conference Publications

  1. Miao Sun, A. Kanani, K. Shroff, and U. Ogras, “LEXI: Lossless Exponent Coding for Efficient Inter-Chiplet Communication in Hybrid LLMs,” Design Automation Conference (DAC), 2026.
  2. “ReVolt: Power Delivery Network-Aware Voltage Droop Control for 2.5D PIM Chiplet Architectures.” CASES 2026, ESWEEK 2026. Accepted.
  3. “Uni-SFU: Algorithm-HW Co-Design for Universal SFUs via Mixed-Degree Piecewise Approximation.” CODES 2026, ESWEEK 2026. Accepted.
  4. Y. Wu, S. Zhou, Miao Sun, and P. Y. Chiang, “dToF LiDAR System Using Addressable Multi-Channel VCSEL Transmitter, 128×80 SPAD Sensor, and ML-Based Object Detection for Adaptive Beam-Steering,” IEEE Custom Integrated Circuits Conference (CICC), 2023.
  5. Miao Sun, Y. Cao, and P. Y. Chiang, “Energy-Aware RetinaFace: A Power-Efficient Edge-Computing SoC for Face Detector in 40 nm,” IEEE International Conference on ASIC (ASICON), 2021.

Mentorship & Teaching Readiness

Mentored graduate students in RTL design methodology, advanced EDA workflows, FPGA verification, and post-silicon bring-up protocols.

  • Digital VLSI Design
  • Computer Architecture
  • Advanced SoC Architecture
  • Hardware Accelerators for Machine Learning
  • Embedded and Edge AI Systems

Professional Service

  • Session Chair, IEEE COINS 2025
  • Reviewer, NeurIPS
  • Reviewer, ECCV
  • Reviewer, IEEE Internet of Things Journal
  • Reviewer, ACM Transactions on Embedded Computing Systems (TECS)

Technical Skills

IC Design: RTL, ASIC flow, synthesis, physical design, timing closure, post-silicon validation
EDA: Cadence, Synopsys, Vivado, FPGA prototyping
Architecture: AI accelerators, chiplet systems, edge AI SoCs, memory hierarchy, interconnects
Programming: Python, C/C++, MATLAB, PyTorch, hardware modeling